1. Field of the Invention
The present invention generally relates to a method and apparatus for reducing contact resistance, and more particularly to a method and apparatus for reducing source/drain series resistance in an ultra-thin silicon-on-insulator metal-oxide-silicon field effect transistor.
2. Description of the Related Art
As silicon-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) channel lengths continue to be aggressively scaled from the 65 nm to the 45 nm node and beyond, it is necessary to reduce the SOI film thickness to suppress short channel effects. However, a consequence of thinner (less than about 30 nm) SOI is increased difficulty in forming low-series resistance source-drain contacts. Not only does the thinner SOI reduce the cross-sectional area normal to the current, but it becomes increasingly difficult to avoid silicidation of the source-drain diffusions from extending completely through the SOI to the back (or buried) oxide (BOX).
It is conventionally known that the source-drain resistance increases sharply when the silicided region reaches the BOX, since the resistance is strongly determined by the interface resistance between the silicide and the single crystal silicon. One presently used solution is to selectively increase the source-drain thickness using a structure known as a “raised source/drain”. A method for forming raised source/drain involves epitaxial-growth, which leads to increasing the gate-to-source and drain overlap capacitance (Miller capacitance) and degraded performance.
Another concern of the conventional art is the possibility of silicide spiking into the junction area, especially at the edges of the channel region.